1. Field
The present inventive concepts relate to a Non-Volatile Memory Express (NVMe), and more particularly to methods, systems, and/or apparatuses for managing input/output (I/O) queues by a Non-Volatile Memory Express (NVMe) controller.
2. Description of the Related Art
Typically, a relatively new interface standard deals with a local non-volatile memory access is Non-Volatile Memory Express (NVMe), sometimes referred to as a Non-Volatile Memory Host Controller Interface Specification. The NVMe is a register-level interface that allows a host application to communicate with a non-volatile memory subsystem. This register-level interface is optimized for enterprise-level and client-level solid state drives (SSDs), which are typically attached to a Peripheral Component Interconnect Express (PCIe) bus interface. The NVMe provides direct input/output (I/O) access to local non-volatile memory. Using NVMe, the latency of read and write operations is reduced compared to the latencies seen while connecting over traditional I/O interfaces, such as Serial-attached Small Computer System Interface (SCSI) or Serial Advanced Technology Attachment (SATA).
However, the present NVM Express specification 1.2 supports 1 to 65,535 I/O queues. During initialization, the host has to send multiple (1 to a maximum of 65,535) create I/O Submission Queue and Create I/O Completion Queue commands to create I/O queues, which highly impacts the time required to initialize the controller. During shut down of the controller, the host has to send multiple (1 to a maximum of 65,535) Delete I/O Submission Queue and Delete I/O Completion Queue commands to delete the previously created I/O queues, which highly impacts the time required to shut down the host controller. For example, an NVMe controller may first fetch the command, process the command, and then sends the response entry to the host NVMe Driver. If the NVMe controller processes the creation or deletion of these commands one by one, it requires a lot of time and resources, and greatly increases the time required to boot up, hibernate, and/or shutdown, the computing device that the NVMe system is installed in, and impacts the amount of power used (e.g., low power conditions).
The above information is presented as background information only to help the reader to understand the present invention. Applicants have made no determination and make no assertion as to whether any of the above might be applicable as Prior Art with regard to the present application.